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AT25080/160/320/640
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080/160/320/640 is divided into four array segments. One
quarter (1/4), one half (1/2), or all of the memory segments can be protected. Any of the data
within any selected segment will therefore be READ only. The block write protection levels and
corresponding status register control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g. WREN, t WC , RDSR).
Table 4. Block Write Protect Bits
Status
Register Bits
Array Addresses Protected
Level
0
1(1/4)
2(1/2)
3(All)
BP1
0
0
1
1
BP0
0
1
0
1
AT25080
None
0300
-03FF
0200
-03FF
0000
-03FF
AT25160
None
0600
-07FF
0400
-07FF
0000
-07FF
AT25320
None
0C00
-0FFF
0800
-0FFF
0000
-0FFF
AT25640
None
1800
-1FFF
1000
-1FFF
0000
-1FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-
protected sections in the memory array are disabled. Writes are only allowed to sections of the
memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
Table 5. WPEN Operation
Protected
Unprotected
Status
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Register
Protected
Writable
Protected
Protected
Protected
Writable
9
0675M–SEEPR–9/03
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